HDL Synthesis : Verilog, VHDL, Tangram

Logic Simulation and Verification : Verilog-XL, Synopsys

Timing Verification :   Motive, Pearl, Veritime

Test Development :   Verifault

Physical Layout :  Silicon Ensemble, Cell3, Cell Ensemble

Physical Verification :  DRACULA (LVS, DRC, ERC, Antenna)

FPGA, CPLD Programming :  Altera and Xilinx Design Flow

Software Support :  C, C++, Perl, Assembler